1. Field of the Invention
The present invention relates generally to electronic circuits for higher voltages and in particular to protect low voltage circuits realized with integrated-circuit technologies. Somewhat more in particular the current invention is also relating to switch controller circuits and more particularly, to integrated circuits for motor bridge interfaces, and even more particularly to circuits controlling MOS power transistors within an H-bridge configuration for DC-motor driving applications.
2. Description of the Prior Art
In many technical fields, where automation is of the utmost importance in order to reach a comfortable and reliable operation for users, like production of modern vehicles, manufacture of electrical and electronical household appliances, data processing or computing devices and telecommunications equipment, or industrial use of precision tooling machines etc. nowadays mixed signal integrated circuits are playing a key role especially when it comes to circuits equally apt for processing data and evaluating signals out of lower and higher voltage ranges within one single chip. The expression ‘mixed signal’ thereby signifying the ability for processing of analog and digital signals by one and the same integrated circuit, which is per se a rather demanding task.
Realizations of the prior art for such circuits are often implemented as specifically tailored semiconductor circuits or chip sets, fulfilling the operational demands regarding the higher voltages or currents supplied. Therefore, when higher voltage operations take place sometimes DMOS (Double Diffused MOS) transistor devices are used, making necessary an expensive process in semiconductor fabrication. Alternatively CMOS devices with extended drain realizations are employed, but when used in a differential input pair transistor configuration, high VGS (Gate-Source) values for the transistors have to be specified, which leads also to more expensive components. Logic circuits or even microprocessor systems normally are working with low voltages. The composition into one chip of these two voltage domains—one for higher, the other for lower voltages—has to be made in such a way, that no detrimental influences are affecting onto each other. Thereto an appropriately combined semiconductor technology capable of handling all these demands is chosen, which also most often leads to costly solutions. The challenge for the designer of such circuits is therefore to find a reliable, efficient and cost effective solution. Using transistors in bipolar or in Double Diffused MOS (DMOS) technology is the current state of manufacture in industry. These technologies are expensive however and it is desirable to find solutions that are less expensive.
In the prior art, there are different technical approaches for achieving the goal of securely operating an integrated circuit under high and low voltage conditions affecting their input pins. However these approaches use often solutions, which are somewhat technically complex and therefore also expensive in production. It would be advantageous to reduce the expenses in both areas. This is achieved by using a voltage supervising technique for the actual input voltage domain acting at the input pins concerned in conjunction with a protection switch for the internal low voltage circuit parts of the chip. The protection switch itself realized as Field Effect Transistor (FET) implemented in extended drain technology. Using the intrinsic advantages of that solution—as described later on in every detail—the circuit of the invention is realized with standard CMOS technology at low cost.
Preferred prior art realizations are implementing protection means differently, more complex in function and more expensive in production. It is therefore a challenge for the designer of such circuits to achieve a high-quality, but lower-cost solution. There are various patents referring to such solutions.
U.S. Pat. No. 6,169,432 (to Sharpe-Geisler) proposes a high voltage switch for providing voltages higher than 2.5 volts with transistors made using a 2.5 volt process whereby a voltage switch is provided made up of 2.5 volt process transistors which tolerate a maximum gate to source, gate to drain, or drain to source voltage of 2.7 volts. The voltage switch transistors are arranged to switch between a voltage, such as 2.5 volts, and a much higher voltage, such as 4.5 volts. In one embodiment of the switch, the voltage switch includes an input provided to the source of an NMOS cascode connected transistor N2. An inverter connects the source of the NMOS cascode N1 to the source of another NMOS cascode N2. A cascode transistor is defined as being connected so that it is turned on and off by varying source voltage with the gate voltage fixed, rather than varying gate voltage. Gates of the cascodes (N1, N2) are connected to Vcc (2.5 volts). PMOS cascode transistors P2 and P3 connect the drains of respective cascode transistors N1 and N2 to PMOS transistors P3 and P4. The PMOS transistors P3 and P4 have sources connected to 4.5 volts. A PMOS transistor P5 has a gate tied to the drain of cascode N2 and provides Vcc to the switch output. A PMOS transistor P6 has a gate tied to the gate of transistor P4 and supplies 4.5 volts to the said switch output. In operation, the switch functions to selectively transition its output between Vcc and 4.5 volts without applying greater than 2.7 volts from the gate to source, gate to drain, or source to drain of any of its transistors.
U.S. Pat. No. 6,181,193 (to Coughlin, Jr.) presents using thick-oxide CMOS devices to interface high voltage integrated circuits, especially a high voltage tolerant CMOS input/output interface circuit. In this circuit, a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.
U.S. Pat. No. 6,452,440 (to Rapp) shows a voltage divider circuit, wherein a charge pump system includes a charge pumping circuit for outputting a high voltage Vpp at a node. An oscillator circuit, coupled to the charge pumping circuit, drives the charge pumping circuit with at least one clock signal. A current source generates a pulldown current. A voltage divider circuit is coupled between the node and the current source. The voltage divider circuit cooperates with the current source to form a feedback loop for controlling the oscillator circuit to run at variable, optimum frequency for controlling the rate-of-rise and the amplitude of the voltage Vpp while minimizing power-supply current drain.
U.S. Pat. No. 6,856,168 (to Oertle et al) introduces a 5 Volt tolerant IO scheme using low-voltage devices wherein systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.
Although these patents and papers describe circuits and/or methods close to the field of the invention they differ in essential features from the method, the system and especially the circuit introduced here.